library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

entity alu is
	generic
	(
		DATA_WIDTH	: natural  := 32;
		CONTROL_WIDTH : natural := 5
	);

	port
	(
		-- Input ports
		aluc	: in  std_logic_vector(4 downto 0);
		a	: in  std_logic_vector(DATA_WIDTH-1 downto 0);
		b   : in  std_logic_vector(DATA_WIDTH-1 downto 0);

		-- Output ports
		result	: out std_logic_vector(DATA_WIDTH-1 downto 0)
	);
end alu;

architecture rtl_alu of alu is
signal utmp: bit_vector(4 downto 0);

begin
	result <= a + b when aluc = "00001" else
			  a - b when aluc = "01001" else
			  a and b when aluc = "00000" else
			  a or b when aluc = "01000" else
			  a xor b when aluc = "11000" else
			  to_stdlogicvector(to_bitvector(b) sll conv_integer(a)) when aluc ="10100" else
			  to_stdlogicvector(to_bitvector(b) srl conv_integer(a)) when aluc ="00100" else
			  to_stdlogicvector(to_bitvector(b) sra conv_integer(a)) when aluc ="01100";

end rtl_alu;
